1. Field of the Invention
The present invention relates to a vertical driving pulse generating circuit and more particularly, to a vertical driving pulse generating circuit of a count down system used in a television receiver or the like.
2. Description of the Prior Art
A vertical driving pulse generating circuit of a count down system is described in Japanese Patent Publication No. 7786/1986. FIG. 1 illustrates the circuit. In FIG. 1, a clock signal having a frequency two times that of a horizontal synchronizing signal supplied to a terminal 1 is frequency-divided into 1/525 by a frequency divider 2. Thus, a frequency-divided output signal having a predetermined pulse width is generated in a terminal 3. In addition, a composite sync signal inputted to a terminal 4 is applied to a vertical synchronizing separation circuit 5, where a vertical synchronizing signal is separated. An NAND gate 6 compares a phase of an output signal (vertical synchronizing signal) of the vertical synchronizing separation circuit 5 with a phase of the frequency-divided output signal of the frequency divider 2. If the phases coincide with each other, an octal counter 7 is reset. When the octal counter 7 is reset, a reset signal selecting circuit 8 receives the frequency-divided output signal of the frequency divider 2 in response to the output of the octal counter 7. Thus, the frequency divider 2 performs precise 1/525 frequency-dividing operation without relying on the vertical synchronizing signal externally applied. Furthermore, when the frequency-divided output signal of the frequency divider 2 and the vertical synchronizing signal are not synchronized with each other, the octal counter 7 counts pulses of the above described vertical synchronizing signal without being reset by the NAND gate 6. When eight pulses are counted, the reset signal selecting circuit 8 receives an output signal of the vertical synchronizing separation circuit 5 in response to the output of the octal counter 7. Thus, the frequency divider 2 performs frequency-dividing operation in response to the vertical synchronizing signal.
Therefore, according to the circuit shown in FIG. 1, if and when the frequency-divided output signal of the frequency divider 2 and the vertical synchronizing signal are asynchronous with each other, eight pulses of the vertical synchronizing signal are counted by the octal counter 7. As a result, when an 8th vertical synchronizing signal arrives, the frequency-divided output signal and the vertical synchronizing signal can be synchronized with each other.
However, in the circuit shown in FIG. 1, a vertical synchronizing signal from a video cassette recorder, a personal computer or the like having no normal vertical period of 262.5H (H is a period of a horizontal synchronizing signal) from a broadcasting station is applied to the terminal 4, there is a problem that synchronization is disturbed. For example, when a vertical synchronizing signal having a pulse width of 3H is applied to the terminal 4 with a period of 262H, it is determined that the phases of the vertical synchronizing signal and the frequency-divided output signal of the frequency divider 2 coincide with each other as a result of comparison of phase by the NAND gate 6, because the pulse width of the vertical synchronizing signal is 3H which is relatively long. Accordingly, the octal counter 7 is reset and the frequency divider 2 is reset with a period of 262.5H in response to the output, so that reproduced pictures gradually shift. As a result, the phases of the signals applied to the NAND gate 6 do not coincide with each other. When the octal counter 7 counts eight pulses of the vertical synchronizing signal, the frequency divider 2 is reset in response to the vertical synchronizing signal. The NAND gate 6 determines that the phases coincide with each other. Thus, the NAND gate 6 repeatedly determines whether or not phases coincide with each other, so that there is a problem that reproduced pictures vertically flow.
Furthermore, in the circuit shown in FIG. 1, if a channel is switched, the phases of the vertical synchronizing signal before switching and after switching do not generally coincide with each other, so that it is determined that the signals are asynchronous with each other. Eight vertical scanning periods (about 133 msec) are required until the frequency divider 2 is reset in response to the vertical synchronizing signal externally applied. Thus, the frequency divider 2 continues to be reset at phase of a vertical synchronizing signal in the previous channel until the frequency divider 2 counts eight pulses of the vertical synchronizing signal, so that the pictures remain shifted. Therefore, every time the channel is switched, a blanking pulse appears on the picture, so that there is a problem that the pictures are unclear.